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i-cube, inc. [rev. 1.6] 2/20/01 1 ocx160 crosspoint switch preliminary data sheet features description the ocx? family of sram-based devices are non-blocking n x n digital crosspoint switches capable of data rates of 667 megabits per second per port. the i/o ports are fixed as either input or output ports. the input ports support flow-through mode only. the output ports are individually programmable to operate in either flow- through (asynchronous) or registered (synchronous) mode. each output register may be clocked by a global clock or a next neighbor clock source. the patented activearray provides greater density, superior performance, and greater flexibility compared to a traditional n:1 multiplexer architecture. the ocx devices support various operating modes covering one input to one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to all outputs while maintaining maximum data rates. in all modes data integrity and connections are maintained on all unchanged data paths. the rapidconfigure parallel interface allows fast configuration of both the output buffers and the switch matrix. readback is supported for device test and verification purposes. the ocx160 also supports the industry standard jtag (ieee 1149.1) interface for boundary scan testing. the jtag interface can also be used to download configuration data to the device and readback data. a functional block diagram of the ocx160 is shown in figure 1. applications figure 1 ocx160 functional block diagram ? 667 mb/s port data bandwidth, >50gb/s aggregate bandwidth low power cmos, 2.5v and 3.3v power supply sram-based, in-system programmable 160 configurable i/o ports ? 80 dedicated differential input ports ? 80 dedicated differential output ports ? supports lvds and lvpecl i/o ? lvttl control interface ? output enable control for all outputs non-blocking switch matrix ? patented activearray ? matrix for superior performance ? double-buffered configuration ram cells for simultaneous global updates ? implieddisconnect ? function for single cycle disconnect/ connect full broadcast and multicast capability ? one-to-one and one-to-many connections ? special broadcast mode routes one input to all outputs at maximum data rate registered and flow-through data modes ? 333 mhz synchronous mode ? 667 mb/s asynchronous mode ? low jitter and signal skew ? low duty cycle distortion rapidconfigure ? parallel interface for configuration and readback jtag serial interface for configuration and boundary scan testing 420 bga package with 1.27mm ball spacing sonet/sdh and dwdm digital cross-connects system backplanes and interconnects high speed test equipment atm switch cores video switching input buffers 80 x 80 crosspoint switch matrix clk oe# hw_rst# update# out[79:0] 160 2 configuration and programming logic rca[6:0] rcb[6:0] rci[3:0] rc_clk# rc_en# 4 7 7 rapidconfigure signals in[79:0] 160 output buffers jtag signals tck trst# tms tdi tdo rco[4:0] 5
ocx160 crosspoint switch ? preliminary data sheet 2 [rev. 1.6] 2/20/01 i-cube, inc. (this page intentionally left blank)
i-cube, inc. [rev. 1.6] 2/20/01 3 ocx160 crosspoint switch ? preliminary data sheet contents 1. introduction ................................................................................................................. .......... 7 1.1 input and output buffers.................................................................................................... .. 8 1.1.1 input and output port function mode ........................................................................... 8 1.1.2 broadcast mode ............................................................................................................ .9 1.2 output buffer configuration ................................................................................................ 9 1.2.1 output control signals................................................................................................... 9 1.2.2 neighboring output port as a clock source .................................................................. 9 1.3 rapidconfigure interface .................................................................................................... 11 1.3.1 rapidconfigure programming instructions.................................................................. 11 1.3.2 implieddisconnect ....................................................................................................... 13 1.4 jtag configuration controller.......................................................................................... 14 1.4.1 jtag interface............................................................................................................ .14 1.4.2 output port configuration ........................................................................................... 14 1.4.3 switch matrix configuration ....................................................................................... 14 1.4.4 mode control register configuration.......................................................................... 14 1.4.5 jtag architecture and shift registers ........................................................................ 15 1.4.6 jtag state machine .................................................................................................... 16 1.4.7 jtag input format ...................................................................................................... 16 1.4.8 jtag instructions ........................................................................................................ 1 7 1.5 device reset options ........................................................................................................ .20 2. pin description .............................................................................................................. .......21 3. differential i/o standards ................................................................................................... 22 3.1 lvds ........................................................................................................................ ......... 22 3.2 lvpecl ...................................................................................................................... ....... 23 3.3 termination resistor packs ................................................................................................ 24 3.4 mixed i/o systems........................................................................................................... .. 24 4. electrical specifications .................................................................................................... ...25 4.1 absolute maximum ratings .............................................................................................. 25 4.2 recommended operating conditions ................................................................................ 25
ocx160 crosspoint switch ? preliminary data sheet 4 [rev. 1.6] 2/20/01 i-cube, inc. 4.3 pin capacitance ............................................................................................................ ..... 25 4.4 dc electrical specifications............................................................................................... 2 6 4.5 ac electrical specifications............................................................................................... 2 7 4.6 timing diagrams............................................................................................................. ... 28 5. package and pinout ........................................................................................................... .. 32 5.1 package pinout .............................................................................................................. ..... 32 5.2 pinout by ball sequence..................................................................................................... 33 5.3 pinout by ball name ......................................................................................................... .36 5.4 package dimensions.......................................................................................................... .38 5.5 package thermal characteristics........................................................................................ 39 6. power consumption ............................................................................................................ 40 6.1 power for lvds i/o ......................................................................................................... .40 6.2 power for lvpecl i/o ..................................................................................................... 41 7. component availability and ordering information ......................................................... 42 8. glossary ..................................................................................................................... ........... 42 9. product status definition .................................................................................................... 44
i-cube, inc. [rev. 1.6] 2/20/01 5 ocx160 crosspoint switch ? preliminary data sheet figures figure 1 ocx160 functional block diagram ......................................................................................... ........... 1 figure 2 ocx160 switch matrix .................................................................................................... .................... 7 figure 3 input and output buffer configuration ................................................................................... ............. 8 figure 4 next neighbor clock block diagram ....................................................................................... ......... 10 figure 5 ocx160 jtag architecture ................................................................................................ .............. 15 figure 6 ocx160 jtag state machine ............................................................................................... ............ 16 figure 7 transmitting lvds signal circuit ........................................................................................ ............. 22 figure 8 receiving lvds signal circuit ........................................................................................... .............. 22 figure 9 transmitting lvpecl signal circuit ...................................................................................... .......... 23 figure 10 receiving lvpecl signal circuit........................................................................................ ............. 23 figure 11 registered output mode timing .......................................................................................... .............. 28 figure 12 flow-through mode timing ............................................................................................... ............... 28 figure 13 output enable timing ................................................................................................... ..................... 28 figure 14 duty cycle distortion.................................................................................................. ....................... 29 figure 15 rapidconfigure write cycle ............................................................................................. ................. 29 figure 16 rapidconfigure read cycle .............................................................................................. ................. 30 figure 17 jtag timing............................................................................................................ .......................... 30 figure 18 typical performance lvds mode .......................................................................................... ........... 31 figure 19 typical performance lvpecl mode........................................................................................ ......... 31 figure 20 ocx160 package pinout .................................................................................................. .................. 32 figure 21 ocx160 package ? bottom, top and side views ............................................................................. 38 figure 22 power consumption diagram for the ocx160 using lvds............................................................. 40 figure 23 power consumption diagram for the ocx160 using lvpecl........................................................ 41
ocx160 crosspoint switch ? preliminary data sheet 6 [rev. 1.6] 2/20/01 i-cube, inc. tables table 1 summary for programmable i/o attributes for ocx160................................................................. 8 table 2 next neighbor outputs.................................................................................................... ................ 10 table 3 rapidconfigure programming instructions .................................................................................. .. 11 table 4 rco[4:0] readback pin assignment......................................................................................... ..... 13 table 5 programming an output buffer using rapidconfigure .................................................................. 13 table 6 mode control register .................................................................................................... ................ 14 table 7 jtag input format ........................................................................................................ ................. 16 table 8 jtag instructions ........................................................................................................ ................... 17 table 9 programming an output using jtag......................................................................................... ..... 19 table 10 number of jtag cycles and configuration time ......................................................................... 19 table 11 device reset options .................................................................................................... .................. 20 table 12 ocx160 pin description.................................................................................................. ............... 21 table 13 termination resistor packs.............................................................................................. ............... 24 table 14 supply voltages and terminating resistors ............................................................................... .... 24 table 15 absolute maximum ratings................................................................................................ ............ 25 table 16 recommended operating conditions........................................................................................ ...... 25 table 17 pin capacitance ......................................................................................................... ...................... 25 table 18 lvttl dc electrical specifications...................................................................................... ........ 26 table 19 lvds dc electrical specifications ....................................................................................... ......... 26 table 20 lvpecl dc electrical specifications ..................................................................................... ...... 26 table 21 ac electrical specifications............................................................................................ ................ 27 table 22 ocx160 pinout by ball sequence.......................................................................................... ........ 33 table 23 ocx160 pinout by ball name .............................................................................................. ......... 36 table 24 package thermal coefficients............................................................................................ ............. 39
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 7 1. introduction the ocx160 is a differential crosspoint-switching device. the main functional block of the device is a switch matrix as shown in figure 1. the switch matrix is a x-y structure supporting an input-to-output data flow. figure 2 shows a conceptual view of the switch matrix with inputs connected to the horizontal trace and outputs to the vertical trace. connections between vertical and horizontal lines are implemented with a proprietary high- performance buffering circuit. signal path delays through the switch matrix are very well balanced, resulting in predictable and uniform pin-to-pin delays. note ? for the purpose of clarity, the logic diagrams within this data sheet are conceptual representations only and do not show actual circuit implementation. figure 2 ocx160 switch matrix the active sram cells are responsible for establishing connections in the switch matrix by turning on the interconnect circuit, while the loading sram cell can be used to store a second configuration that can be transferred to the active sram cell at a later time. the two sram cells are arranged so that a double buffered scheme can be employed. through the use of an internal signal (generated automatically during a programming cycle) it is possible to store a second configuration map in the loading sram while the active sram maintains its present connection status. when the update# signal is asserted low, the contents of the loading sram cell are transferred to the active sram cell and the switch matrix connection is either made or broken. the update# signal can be used to control when the switch matrix is reconfigured. for instance, as long as the update# signal is asserted high, the loading sram cells for the entire switch matrix could be changed without affecting the current configuration of the switch. when the update# signal is asserted low, the entire switch matrix would be reconfigured simultaneously. if the update# signal is asserted continuously, all crosspoint programming commands (generated by rapidconfigure or jtag programming cycles) will take effect immediately, since the loading sram cell ? s contents will be transferred directly to the active sram cell. update# active sram cell loading sram cell data proprietary high-performance buffering circuit
ocx160 crosspoint switch ? preliminary data sheet 8 [rev. 1.6] 2/20/01 i-cube, inc. 1.1 input and output buffers all of the input buffers are differential inputs with flow-through mode. the output buffers are programmable for either flow-through or registered mode. figure 3 shows the basic block diagram of the input and output blocks with the sources for the output control signals (oe# and clk). the control signals are explained in more details in the following sections. figure 3 input and output buffer configuration 1.1.1 input and output port function mode the following legend describes the various modes of the input and output ports and the specification used by the ocxpro ? software. legend: ax ? switch matrix signal px ? port signal oe# ? output enable (# means ? active low ? ) clk ? clock table 1 summary for programmable i/o attributes for ocx160 symbol i/o port function mnemonic input ? the external signal is buffered from the input port pin to the corresponding switch matrix line. in output ? the internal signal is buffered from the corresponding switch matrix line to the output port pin. in this mode an optional output enable (oe#) can be selected. the default state is logic high with enable set to on. op registered output ? the internal signal on the switch matrix line is registered by an edge-triggered register within the output port. a clock source is required in this mode. an output enable (oe#) is available but not required. ro no connect ? in this mode, the output port pin is isolated from the switch matrix. nc clk switch matrix input d q next neighbor output oe# output mode select clock select px ax oe# px ax clk d q oe# px ax ax px
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 9 1.1.2 broadcast mode the ocx160 has a special broadcast mode which connects any input to all outputs without performance degradation. the input is selected using rapidconfigure or jtag and disconnects all other inputs. the global update pin (update#) must be held high during broadcast mode. asserting the update# pin returns the array to the previous program condition. 1.2 output buffer configuration every output port of the ocx160 can be configured as either a flow-through or registered output. in registered mode there are two clock sources that are available: global clock next neighbor additionally, there are output control signals. 1.2.1 output control signals every output port of the ocx has a global output enable signal (oe#). all output buffers have output enables that have programmable polarity and are individually configurable. additionally each output can be permanently enabled (always on) or disabled (always off) which is useful for applications which need to tri-state outputs (for example when using multiple chips in expansion mode) or for power saving in designs that do not need to use all the outputs available. two control bits are used to control the function of the output enable function as described in table 5. 1.2.2 neighboring output port as a clock source a physically adjacent port can be used as a clock source for an output port configured in registered mode. these outputs are grouped in pairs such that the signal being switched through out0 can be used to clock the signal being switched through out1, and vice versa. any single clock or data input signal can be used to clock any other input signal provided they are switched to an appropriate output pair (see table 2). figure 4 shows the implementation of next neighbor output port clocking in the ocx160 switch. for example, in x is used for data input while in y is used for the corresponding clock. in x is connected to out0 via the crosspoint array while in y is connected to out1 via the crosspoint array. out0 is configured in registered output (ro) mode with out1 as its next neighbor clock selection. out1 will output the clock signal as well as clock the data in out0. adjacent port selection is required for next neighbor clocking in the registered output mode. this feature is useful in many applications where different types of data switching through the crosspoint array have various associated clocks. to match the delays in the data and corresponding clocks, it is common practice to pass the clocks through the switch along with the data.
ocx160 crosspoint switch ? preliminary data sheet 10 [rev. 1.6] 2/20/01 i-cube, inc. figure 4 next neighbor clock block diagram the advantages of next neighbor clocking are: 1. using next neighbor clocking in the registered output (ro) mode helps reduce the skew in outgoing data. 2. for a design with a large number of outputs switching simultaneously, next neighbor clocking mode is useful to stagger outputs for reduced board noise caused by simultaneous switching outputs. note ? selecting the next neighbor clock for both outputs at the same time is not recommended. only one output in the pair at a time can be clocked by its next neighbor. only out1 can neighbor with out0, out3 with out2, etc. out2 cannot neighbor with out1, or out4 with out3, etc. table 2 next neighbor outputs pairing sequence for neighboring outputs output next neighbor pairs 0,1 2,3 4,5 6,7 8,9 ? ? ? ? 76,77 78,79 clk d q next neighbor out0 oe# crosspoint array clk d q next neighbor oe# out1 clock select clock select output mode select output mode select any input port (in x ) any input port (in y )
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 11 1.3 rapidconfigure interface rapidconfigure (rc) is a 25 signal parallel interface that is used to program the ocx160 device. the 25 pins are allocated as follows: rca[6:0] = rapidconfigure address a. rca are input pins. rcb[6:0] = rapidconfigure address b. rcb are input pins. rci[3:0] = rapidconfigure instruction bits rco[4:0] = rapidconfigure readback. rco are output pins. rc_clk# = rapidconfigure clock (negative edge clock) rc_en# = rapidconfigure cycle enable (active low) 1.3.1 rapidconfigure programming instructions the rc interface supports both write and read types of operations: 1. write operations (reset crosspoint and input or output buffer (iob), configure an output buffer, connect/disconnect crosspoint) 2. read operations (output buffer and crosspoint configuration read). table 3 rapidconfigure programming instructions rci[3:0] rca[6:0] rcb[6:0] rco[4:0] instruction description 0000 reserved 0001 reserved 0010 x x reset crosspoint array reset the entire crosspoint array to no connect. all output buffers remain unchanged by this operation. 0011 x input port address set array to broadcast mode connects the input selected by rcb[6:0] to all output ports and disconnects all other inputs. the global update (update#) pin must be held high during broadcast mode. activating the global update pin returns the array to the previous program condition. 0100 output port address data configure an output buffer program an output buffer specified by rca[6:0]. see table 5 for rcb[6:0] bit assignment and buffer functionality. 0101 readback crosspoint, output buffer status this is a two-cycle instruction. cycle 1 output port address intput port address x specify the crosspoint connect status at input location specified by rca[6:0] to the output location specified by rcb[6:0].
ocx160 crosspoint switch ? preliminary data sheet 12 [rev. 1.6] 2/20/01 i-cube, inc. note ? x = don ? t care. cycle 2 x x output data readback (using rco[4:0]) the status of the input buffer specified in cycle 1 by rca[6:0], the output buffer specified in cycle 1 by rco[4:0] and the crosspoint connect status. see table 4 for rco[4:0] readback pin assignment. 0110 x x update program the global update function without the use of the update# pin. 0111 x input port address disconnect input disconnect the crosspoint cells of the input row location specified by rca[6:0]. 1000 output port address input port address disconnect input and output disconnect the crosspoint cell at the input location specified by rca[6:0] to the output location specified by rcb[6:0]. all other connections from the source input address or to the same output address remain the same as before. 1001 output port address input port address connect, with implieddisconnect connect the crosspoint cell at the input location specified by rca[6:0] to the output location specified by rcb[6:0]. all other connections from the same input address or to the same output address are set to no connect (nc). 1010 output port address input port address connect, without implieddisconnect connect the crosspoint cell at the input location specified by rca[6:0] to the output location specified by rcb[6:0]. all other connections from the same input address remain the same as before. 1011 reserved 1100 reserved 1101 x x reset all reset the switch matrix to no connects (nc). output buffers default to flow- through mode (op) with output enable set to always enabled (on). output buffer defaults to select global clock (clk) source even though mode is op. 1110 reserved 1111 reserved table 3 rapidconfigure programming instructions (continued) rci[3:0] rca[6:0] rcb[6:0] rco[4:0] instruction description
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 13 1.3.2 implieddisconnect implieddisconnect is a feature that provides the ability to make fast switch connection changes. when using the rc instruction ? connect, with implieddisconnect ? to establish a new connection, any existing connection to that output port is automatically broken. thus, a connection change, i.e. breaking an existing connection and then making a new one, can be accomplished in one rapidconfigure cycle. table 4 rco[4:0] readback pin assignment rco[4:0] readback location signal/function o4 crosspoint connection status: 0 = no connection (nc) ? (default state at reset) 1 = connected o3 output buffer clock select: 0 = global clock ? (default state at reset) 1 = next neighbor o2 output buffer output mode: 0 = flow-through (op) ? (default state at reset) 1 = registered (ro) o1, o0 0,0 0,1 1,0 1,1 output buffer output enable: output enabled (on) ? this is the default state at reset output disabled (off) output controlled by oe (active high) output controlled by oe# (active low) table 5 programming an output buffer using rapidconfigure rcb[6:0] signal/function b6, b5, b4 don ? t care b3 clock select: 0 = global clock 1 = next neighbor b2 output mode: 0 = flow-through (op) 1 = registered (ro) b1, b0 0,0 0,1 1,0 1,1 output enable: output enabled (on) ? this is the default state at reset output disabled (off) output controlled by oe (active high) output controlled by oe# (active low)
ocx160 crosspoint switch ? preliminary data sheet 14 [rev. 1.6] 2/20/01 i-cube, inc. 1.4 jtag configuration controller the output port attributes and the switch matrix connections can be programmed using the jtag serial bus. the rapidconfigure interface can be enabled or disabled using the jtag serial bus. the jtag ? based serial mode is always available for configuration regardless of whether the rapidconfigure mode is enabled or disabled. however, proper care must be taken when switching between jtag and rapidconfigure for configuring the devices. before attempting to change switch matrix connections or output port configuration through jtag, the user must first ensure that the rapidconfigure mode is disabled by using jtag serial mode to set the rce bit to zero in the mode control register. 1.4.1 jtag interface the dedicated jtag tap interface is designed in compliance with the ieee-1149.1. the standard interface has five pins: test data out (tdo), test mode select (tms), test data in (tdi), test reset (trst#), and test clock (tck), which allow boundary scan testing as well as device configuration and verification. the i-cube supplied software will automatically generate the necessary bitstream from a higher-level textual description of the required configuration. data on the tdi and tms pins are clocked into the device on the rising edge of the tck signal, while the valid data appears on the tdo pin after the falling edge of tck. for more detailed information on jtag programming, refer to the ocx160 register programming manual . 1.4.2 output port configuration output port configuration is accomplished by loading the appropriate bitstream into the programming registers present at each output port. the jtag serial bus is used to load configuration data into the output port programming registers, one output port at a time. 1.4.3 switch matrix configuration the contents of the sram cells controlling switch matrix connection can be modified using the jtag. this is accomplished by loading the configuration data, one word at a time, into the sram cells in the switch matrix. 1.4.4 mode control register configuration the ocx160 contains a single bit mode control register used to store user flags for rapidconfigure enable (rce). these are required for proper functioning of the device. the contents of this register can be changed using the jtag interface and a special jtag instruction. table 6 mode control register rce mode 0 rapidconfigure interface disabled (off) 1 rapidconfigure interface enabled (on)
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 15 1.4.5 jtag architecture and shift registers figure 5 ocx160 jtag architecture jtag data register - 1 bit boundary scan register (189 x 2 = 378 bits) tap controller tdi instruction register - 16 bits tdo tms tck device identification register - 32 bits bypass register - 1 bit trst# mode control register - 1 bits jtag address register - 7 bits buf mux
ocx160 crosspoint switch ? preliminary data sheet 16 [rev. 1.6] 2/20/01 i-cube, inc. 1.4.6 jtag state machine figure 6 ocx160 jtag state machine 1.4.7 jtag input format table 7 jtag input format instruction data address a bit number 15141312111098765432 10 bit name i3 i2 i1 i0 bb ba b9 b8 b7 a6 a5 a4 a3 a2 a1 a0 test logic reset run test/ idle select dr scan capture dr shift dr exit 1 dr pause dr exit 2 dr update dr select ir scan capture ir shift ir exit 1 ir pause ir exit 2 ir update ir 0 0 0 0 0 0 0 0 0 1 11 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 17 1.4.8 jtag instructions table 8 jtag instructions i [3:0] bb ba b9 b8 b7 a6-a0 instruction description 0 0 0 0 x x x x x x sample/extest places the device in scan mode. 0 0 0 1 x x x x x x sample/extest places the device in scan mode. 0 0 1 0 x x x x x x reset the crosspoint array resets the entire crosspoint array to no-connect. all other output buffer configurations are unchanged by this operation. 0 0 1 1 x x x x x x set array for broadcast mode use the jtag address register as the input address to be the broadcast input connects the selected input to all output cells and disconnects all other inputs. activating the global update jtag instruction returns the crosspoint array from the broadcast mode to the previous programed state. 0100 x clock select data mode oe oe output buffer address program a buffer programs the output buffer address specified in the jtag instruction (a6-a0). the configuration data is also specified in the jtag instruction bits ba-b7. see table 9 for bit assignment of the buffer functionality. 0 1 0 1 x x x x x output address/ buffer configuration readback readback the connectivity of the crosspoint cell with the input location specified in the jtag address register and the output location specified jtag instruction (a0-a6). it also returns the configuration of the output buffer addressed in the jtag instruction (a0-a6). the readback data is shifted out of tdo in the following sequence: 1. crosspoint connect (1=connected, 0=no connection) 2. output enable ? b7 (see table 9) 3. output enable ? b8 (see table 9) 4. output data source ? b9 (0=flow-through, 1=registered) 5. output clock select ? ba (0=global clock, 1=next neighbor) 6. state of broadcast bit 7. state of the rce bit note: this instruction does not increment the jtag address register. this instruction also requires two dr cycles 0 1 1 0 x x x x x x update the crosspoint array update the programmed connection from the loading sram to the active sram. 0 1 1 1 x x x x x x disconnect input cell disconnect the crosspoint connections from the input address specified in the jtag address register.
ocx160 crosspoint switch ? preliminary data sheet 18 [rev. 1.6] 2/20/01 i-cube, inc. 1 0 0 0 x x x x x output address disconnect input and output disconnect the crosspoint cell at the input location specified at the jtag address register and the output location specified in the disconnect jtag instruction (a6-a0). all other connections from the same input address or to the same output address remain the same. 1 0 0 1 x x x x x output address connect with implieddisconnect connects the crosspoint cell at the input location specified on the jtag address register and the output location specified in the connect jtag instruction (a6-a0). all other connections from the same input address or the same output address are set to no-connects. note: this instruction increments the jtag address register (input address). 1 0 1 0 x x x x x output address connect ? no implieddisconnect connects the crosspoint cell at the input address specified in the jtag address register and the output address specified in the connect jtag instruction (a6-a0). all other connections from the same input remain the same as before. 1 0 1 1 x x x x x input address set the jtag address register sets the 7-bit jtag address register with the 7-bit address (a6-a0) of the jtag instruction register. the 7-bit address of the jtag address register becomes the input port address for crosspoint access. 1 1 0 0 x x x x x x device id out serialize the device id and revision history out to tdo. id for the ocx160 is 0x0000b89f 1 1 0 1 x x x x x x reset output buffer and crosspoint array resets the crosspoint array to no-connects. sets the output buffer to flow-through mode with output enabled. the device id is serialized to tdo. 1 1 1 0 x x x x x x set rce bit sets the rce bit of the mode control register with the jtag instruction bit a0. to turn on the rce bit, encode bit a0 to 1. to turn off the rce bit, encode bit a0 to 0. 1 1 1 1 x x x x x x bypass places device in a mode to pass tdi data to tdo with one clock delay. used for programming and testing devices through serial connected jtag controls. table 8 jtag instructions (continued) i [3:0] bb ba b9 b8 b7 a6-a0 instruction description
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 19 table 9 programming an output using jtag ba, b9, b8, b7 signal/function ba clock select: 0 = global clock 1 = next neighbor b9 output mode: 0 = flow-through (op) 1 = registered (ro) b8, b7 0,0 0,1 1,0 1,1 output enable: output enabled (on) ? this is the default state at reset output disabled (off) output controlled by oe (active high) output controlled by oe# (active low) table 10 number of jtag cycles and configuration time operation ocx160 jtag cycles jtag reset sequence (tms = ? 11111 ? )7 enable or disable rapidconfigure 28 change attributes of one output port 28 change attributes of all output ports 2,240 reset jtag controller + reset all output ports + clear all sram cells 35 connect or disconnect two ports 56 configure entire switch matrix 181,440 completely configure the device (all output ports and all switch matrix connections) 183,680
ocx160 crosspoint switch ? preliminary data sheet 20 [rev. 1.6] 2/20/01 i-cube, inc. 1.5 device reset options the power-on reset, rapidconfigure reset, hardware reset, and jtag reset functions will program the output buffers to flow-through mode (with global clock selected), and output enabled (on). jtag can be reset via the trst# pin or by clocking five consecutive one to the tms pin. the hardware reset pin can be done accomplished through the hw_rst# pin (active low). rc reset can be accomplished by applying the rc instruction 1101 to the rci[3:0] pins. table 11 device reset options programming interface reset method output ports switch matrix rce mode control jtag tap hardware reset power-on reset op nc 1 (rc enabled) tlr 1 1. tlr = test logic reset state. hw_rst# (low pulse) op nc 1 (rc enabled) tlr jtag reset 1. low pulse on trst# unchanged unchanged unchanged tlr 2. tms high for 5 tclk cycles unchanged unchanged unchanged tlr 3. device reset (instruction 1101) op nc 1 (rc enabled) tlr 4. reset crosspoint array (instruction 0010) unchanged nc unchanged unchanged rapidconfigure reset 1. device reset (instruction 1101) op nc 1 (rc enabled) unchanged 2. reset crosspoint array (instruction 0010) unchanged nc unchanged unchanged
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 21 2. pin description notes : 1. dedicated differential input buffers can receive both lvds and lvpecl voltage levels using 3.3v supply. 2. v dd .pad is 2.5v for lvds outputs or 3.3v for lvpecl outputs. 3. dedicated differential output buffers can be biased using different supplies for v dd .pad and external resistors to support both lvds and lvpecl output voltage levels. 4. the lvttl control, jtag pins, and differential input ports are 3.3v ? they are not 5v tolerant. 5. the differential output pins powered from 2.5v are 3.3v tolerant. table 12 ocx160 pin description pin name # of pins type description inp[79:0] 80 input non-inverting differential input signals inn[79:0] 80 input inverting differential input signals outp[79:0] 80 output non-inverting differential input signals outn[79:0] 80 output inverting differential input signals clkp 1 input non-inverting differential global clock clkn 1 input inverting differential global clock oe# 1 input global output enable hw_rst# 1 input hardware reset update# 1 input global update rc pins rca[6:0] 7 input rapidconfigure address a rcb[6:0] 7 input rapidconfigure address b rco[4:0] 5 output rapidconfigure readback rci[3:0] 4 input rapidconfigure instruction bits rc_clk# 1 input rapidconfigure clock rc_en# 1 input rapidconfigure cycle enable jtag pins tck 1 input jtag test clock tms 1 input jtag test mode select tdi 1 input jtag test data in trst# 1 input jtag test reset tdo 1 output jtag test data out power and ground pins v dd .core 12 2.5v power core voltage v dd .pad (2, 3) 8 2.5v or 3.3v power differential output buffer voltage v dd .in (1, 4) 8 3.3v power lvttl control pins voltage and differential input buffer voltage v ss 36 ground ground
ocx160 crosspoint switch ? preliminary data sheet 22 [rev. 1.6] 2/20/01 i-cube, inc. 3. differential i/o standards the ocx160 support the two most popular differential signaling standards: low voltage differential signaling (lvds) and low voltage positive emitter coupled logic (lvpecl). lvds is typically used in communication systems as high speed, low noise point-to-point links. the ocx160 conforms to the ansi/tia/eia-644 standard covering electrical specifications for output drivers and receiver inputs. lvpecl is commonly used in video switching applications or those designs requiring transmission of high- speed clock signals. 3.1 lvds lvds is a differential signaling standard. it requires that one data bit is carried through two signal lines. as with all differential signaling standards, lvds has an inherent noise immunity over single-ended standards. the voltage swing between two signal lines is approximately 350mv. the use of a reference voltage or a board termination voltage is not required. lvds requires the use of two pins per input or output. lvds requires external resistor termination. transmitting and receiving circuits for lvds are shown in figures 7 and 8. figure 7 transmitting lvds signal circuit figure 8 receiving lvds signal circuit v dd .pad=2.5v lvds output 2.5v data transmit ocx device to lvds receiver to lvds receiver 165 165 outp r div 140 z 0 =50 ? z 0 =50 ? r s r s outn data recieve ocx device z 0 =50 ? z 0 =50 ? from lvds driver inp 100 r t inn ? +
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 23 3.2 lvpecl lvpecl is another differential signaling standard that specifies two pins per input or output. the voltage swing between these two signal lines is approximately 850 mv. the use of a reference voltage or a board termination voltage is not required. the lvpecl standard requires external resistor termination. transmitting and receiving circuits for lvpecl are shown in figures 9 and 10. figure 9 transmitting lvpecl signal circuit figure 10 receiving lvpecl signal circuit 3.3v data transmit ocx device to lvpecl receiver to lvpecl receiver 100 100 outp r div 187 z 0 =50 ? z 0 =50 ? r s r s outn v dd .pad=3.3v lvpecl output data recieve ocx device inp z 0 =50 ? z 0 =50 ? from lvpecl driver 100 r t ? + inn
ocx160 crosspoint switch ? preliminary data sheet 24 [rev. 1.6] 2/20/01 i-cube, inc. 3.3 termination resistor packs resistor packs are available with the values and the configuration required for lvds and lvpecl termination from bourns, inc. the part numbers are listed in table 13. for pricing and availability questions, please contact them directly at www.bourns.com. 3.4 mixed i/o systems the use of different supply voltages and terminating resistors allows the ocx160 to support lvds / lvpecl translation as well as switching as outlined in table 14. notes : 1. v dd .in = 3.3v 10%, v dd .core = 2.5v 5% 2. it is not possible to mix lvds and lvpecl outputs on a device table 13 termination resistor packs bournes part number differential i/o standard termination for: pairs per pack no. of pins cat16-lv2f6 lvds driver 2 8 cat16-lv4f12 lvds driver 4 16 cat16-pc2f6 lvpecl driver 2 8 cat16-pc4f12 lvpecl driver 4 16 cat16-pt2f2 lvds/lvpecl receiver 2 8 cat16-pt4f4 lvds/lvpecl receiver 4 16 table 14 supply voltages and terminating resistors input output v dd .pad r t r s r div lvds lvds 2.5v 100 ? 165 ? 140 ? lvpecl lvds 2.5v 100 ? 165 ? 140 ? lvds lvpecl 3.3v 100 ? 100 ? 187 ? lvpecl lvpecl 3.3v 100 ? 100 ? 187 ?
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 25 4. electrical specifications 4.1 absolute maximum ratings 4.2 recommended operating conditions 4.3 pin capacitance 1. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. a maximum undershoot of 2v for a maximum duration of 20 ns is acceptable. overshoot to 3.6v is acceptable. 3. all inputs are 3.3v tolerant with the v dd pin at 2.5v or 3.3v. 4. note that min and max values for v dd for differential outputs are i/o standard dependent. 5. capacitance measured at 25 c. sample tested only. 6. measured using human body model. table 15 absolute maximum ratings 1 symbol parameter limits units v dd .core supply voltage (core) -0.3 to +3.0 v v dd .in supply voltage (inputs) -0.3 to +3.6 v v dd .pad supply voltage (differential outputs) -0.3 to +3.6 v v in 2 input voltage -0.3 to +3.6 3 v t j junction temperature +150 c t stg storage temperature -65 to +150 c p max maximum power dissipation 6 w esd 6 electrostatic discharge 2000 v table 16 recommended operating conditions symbol parameter limits units v dd .core supply voltage (core) +2.375 to +2.625 v v dd .pad 4 supply voltage (differential output buffers) 3.3v 10% to 2.5v 5% v v dd .in supply voltage (inputs) +3.0 to +3.6 v t a operating temperature: commercial operating temperature: industrial 0 to +70 -40 to +85 c table 17 pin capacitance 5 symbol parameter max units c pin signal pin capacitance 10 pf
ocx160 crosspoint switch ? preliminary data sheet 26 [rev. 1.6] 2/20/01 i-cube, inc. 4.4 dc electrical specifications (t a = -40 c to 85 c, v dd .in = 3.3v 10%, v dd .core = 2.5v 5%) 1. all lvttl input pins have pull-up resistors. 2. see section 6 for dynamic power consumption calcualtion. 3. refer to figures 7 and 8 for termination resistor. 4. refer to figures 9 and 10 for termination resistor. 5. maximum capacitive load is 12 pf. these values in table 20 are valid at the output of the source termination pack, as shown in sections 3.2 and 3.3, with a 100 ? differential load only. the v oh levels are 200mv below lvpecl levels and are compatible with devices tolerant of lower common-mode ranges. the above table summarizes the dc output specifications of lvpecl. table 18 lvttl dc electrical specifications symbol parameter conditions min max units v ih high-level input ports are 3.3v tolerant 2.0 3.6 v v il low-level input ports are 3.3v tolerant -0.3 0.8 v v oh high-level output v dd .pad = min i oh = -4ma 2.4 v dd .pad+ 0.3 v v ol low-level output v dd .pad = min i ol = 8ma 0.4 v il ih , il il (1) input pin leakage current v dd .in= max 0.0 < in < v dd.pad +5 -50 ? il oz tristate leakage output off state v dd .pad = max 0.0 < in < v dd.pad +5 -5 ? power p ddq (2) quiescent power all v dd = max 0.5 w table 19 lvds dc electrical specifications dc parameter min typ max units output high voltage for outp and outn (3) 1.6 v output low voltage for outp and outn 0.90 v differential output voltage (5) 250 350 450 mv output common-mode voltage 1.125 1.25 1.375 v differential input voltage 100 350 mv input common-mode voltage 0.25 1.25 2.25 v table 20 lvpecl dc electrical specifications dc parameters min max v ih (4) v dd .pad - 1.165 v dd .pad - 0.880 v il v dd .pad - 1.810 v dd .pad - 1.475 v oh 1.80 2.40 v ol 0.95 1.55
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 27 4.5 ac electrical specifications (v dd .in = 3.3v 10%, v dd .core = 2.5v 5%) notes : 1. these parameters are guaranteed but not tested in production. table 21 ac electrical specifications 0 c to 70 c -40 c to +85 c symbol parameter min max min max units r data nrz data rate (1) 667 667 mb/s f ro registered output clock frequency (1) 333 333 mhz t w_ro registered clock pulse width, high or low (1) 22ns t s_ro registered output setup time to clock 4 4 ns t h_ro registered output clock to hold data 0 0 ns t co_ro registered output clock to data out valid 2.5 2.5 ns t phl , t plh one way signal propagation delay, fanout = 1 5.5 6.5 ns t w+ input flow-through positive pulse width 1.5 1.5 ns t w- input flow-through negative pulse width 1.5 1.5 ns t dcd+ , t dcd- duty cycle distortion 0.5 0.6 ns t jitter output jitter tbd tbd tbd tbd ps t sk skew between output ports (1) 0.5 0.6 ns t phz_ot , t plz_ot output enable to valid data 3 3 ns t pzh_ot , t pzl_ot output enable to high z state 3 3 ns t rc rapidconfigure clock period 12 12 ns t w+_rc t w-_rc rapidconfigure clock pulse width 5 5 ns t s_rc rapidconfigure address setup to rc_clk# 3 4 ns t h_rc rapidconfigure address and enable hold time to rc_clk# 3 4 ns t p_ud update of crosspoint to data out 10 10 ns f jtag jtag clock frequency (tck) 20 20 mhz t w_jtag jtag clock pulse width (tck) @ 20mhz cycle 20 30 20 30 ns t s_jtag jtag setup time 4 4 ns t h_jtag jtag hold time 0 0 ns t p_jtag jtag clock to output data valid (tdo) 20 20 ns
ocx160 crosspoint switch ? preliminary data sheet 28 [rev. 1.6] 2/20/01 i-cube, inc. 4.6 timing diagrams note ? for the purpose of clarity, the timing diagrams within this data sheet are conceptual representations only and do not show actual circuit implementation. figure 11 registered output mode timing figure 12 flow-through mode timing figure 13 output enable timing t co_ro d n-1 d n d n+1 d n d n+1 outport t w_ro t w_ro t s_ro t h_ro clk inport inport outport ro in switch matrix dq clk inport 1 inport 2 outport 1 outport 2 t sk t sk t plh t w+ t phl inport 1 in op outport 1 switch matrix inport 2 outport 2 oe# outport t pzh_ot t pzl_ot t plz_ot t phz_ot inport oe# in op outport inport switch matrix
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 29 figure 14 duty cycle distortion figure 15 rapidconfigure write cycle inport t in+ outport t in- t out+ t out- t dcd+ =t in+ - t out+ t dcd- =t in- - t out- in op switch matrix outport inport rca/rcb address, instruction rc_en# t rc t w+_rc t s_rc t rc t w-_rc t h_rc t s_rc t h_rc rc_clk#
ocx160 crosspoint switch ? preliminary data sheet 30 [rev. 1.6] 2/20/01 i-cube, inc. figure 16 rapidconfigure read cycle figure 17 jtag timing rca/rcb address, instruction rc_en# t rc t w+_rc t s_rc t rc t w-_rc t h_rc t s_rc t h_rc rc_clk# high impedance data valid rco t p_jtag t s_jtag t h_jtag t w_jtag t w_jtag tck tdi, tms tdo
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 31 figure 18 typical performance lvds mode figure 19 typical performance lvpecl mode typical performance at 667 mb/s with prbs data (currently not available for this document) typical performance at 667 mb/s with prbs data (currently not available for this document)
ocx160 crosspoint switch ? preliminary data sheet 32 [rev. 1.6] 2/20/01 i-cube, inc. 5. package and pinout 5.1 package pinout figure 20 ocx160 package pinout a b c d e f g h k l j m n p r t u v w ab 1 2 3 4 5 6 7 8 9 10111213141516 171819 202122232425 26 rci1 rcb6 rc_en# rci0 rci3 ad ac aa ae af y rcb5 rcb4 rc_clk# rci2 rco4 hw_rst# update# tdi trst# tck tdo tms clkp clkn rco3 rco2 rca1 rca0 oe# rco1 rco0 rca5 rca2 rcb0 rcb2 rcb1 rca3 rca6 rcb3 rca4 top view ocx160 in 420 bga package out79p out79n out78p out78n out75p out75n out74n out73n out72n out67n out74p out73p out72p out67p out66p out65p out66n out69n out69p out70p out76p out77p out77n out76n out71p out71n out68n out70n out68p out63p out61p out65n out63n out62p out54n out60n out55n out54p out53p out55p out60p out61n out64n out59n out58n out57n out56n out64p out59p out58p out57p out56p out62n out51n out51p out53n out52p out52n out46p out45p out44n out44p out46n out47n out47p out50n out49n out48n out43n out42n out50p out49p out48p out43p out42p out41p out45n out40p out41n out40n out39n out39p out38n out38p out35n out35p out34p out33p out32p out27p out34n out33n out32n out27n out26n out25n out26p out29p out29n out30n out36n out37n out37p out36p out31n out31p out28p out30p out28n out23n out25p out23p out22n out14p out20p out15p out14n out13n out15n out20n out21p out24p out19p out18p out17p out16p out24n out19n out18n out17n out16n out22p out11p out11n out13p out12n out12p out06n out05n out04p out04n out06p out07p out07n out10p out09p out08p out03p out02p out10n out09n out08n out03n out02n out01n out05p out00n out01p out00p in40n in41n in42n in43n in48n in49n in50n in51n in56n in57n in58n in59n in64n in65n in66n in67n in72n in73n in74n in75n in76n in77n in77p in76p in75p in74p in73p in72p in67p in66p in65p in64p in59p in58p in57p in56p in51p in50p in49p in48p in43p in42p in41p in40p in44n in44p in45n in45p in47p in46n in46p in47n in52p in52n in53p in53n in54n in54p in55p in55n in60n in60p in61p in61n in62n in62p in63p in63n in68n in68p in69n in69p in70p in70n in78p in71n in79p in78n in79n in71p in31p in00n in01n in02n in03n in08n in09n in10n in11n in16n in17n in18n in19n in24n in25n in26n in27n in32n in33n in34n in35n in36n in37n in37p in36p in35p in34p in33p in32p in27p in26p in25p in24p in19p in18p in17p in16p in11p in10p in09p in08p in03p in02p in01p in00p in04n in04p in05n in05p in07p in06n in06p in07n in12p in12n in13p in13n in14n in14p in15p in15n in20n in20p in21p in21n in22n in22p in23p in23n in28n in28p in29n in29p in30p in30n in38p in31n in39p in38n in39n nc out21n 1 2 3 4 5 6 7 8 9 10111213141516171819 202122232425 26 a b c d e f g h k l j m n p r t u v w ab ad ac aa ae af y vss vdd.core vdd.pad vdd.in vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vdd.core vdd.core vdd.core vdd.core vdd.core vdd.core vdd.core vdd.core vdd.core vdd.core vdd.core vdd.pad vdd.pad vdd.pad vdd.pad vdd.pad vdd.pad vdd.pad vdd.in vdd.in vdd.in vdd.in vdd.in vdd.in vdd.in 0-39 inputs 40-79 inputs 40-79 outputs 0-39 outputs
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 33 5.2 pinout by ball sequence table 22 ocx160 pinout by ball sequence ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name a1 v ss b1 rc_clk# c1 out78p d1 out79p e1 out75p a2 v ss b2 v ss c2 out78n d2 out79n e2 out75n a3 in40n b3 in40p c3 v ss d3 rc_en# e3 rcb4 a4 in41n b4 in41p c4 rci2 d4 v ss e4 rcb5 a5 in42n b5 in42p c5 rci3 d5 rci1 e5 v ss a6 in44n b6 in44p c6 in43p d6 in43n e6 rci0 a7 in48n b7 in48p c7 in45n d7 in45p e7 v dd .in a8 in49n b8 in49p c8 in47p d8 in46n e8 in46p a9 in51n b9 in51p c9 in47n d9 in52p e9 v dd .core a10 in56n b10 in50p c10 in50n d10 in52n e10 v dd .core a11 in56p b11 in53p c11 in53n d11 in54n e11 in54p a12 in57n b12 in57p c12 in55p d12 in55n e12 v dd .in a13 in58p b13 in58n c13 in60n d13 in60p e13 v ss a14 in64n b14 in64p c14 in61p d14 v ss e14 v ss a15 in59p b15 in59n c15 in61n d15 in62p e15 in62n a16 in65n b16 in65p c16 in63p d16 in63n e16 v dd .in a17 in66p b17 in66n c17 in68p d17 in68n e17 v ss a18 in67n b18 in67p c18 in69p d18 in69n e18 v dd .core a19 in70p b19 in70n c19 in71p d19 in71n e19 v dd .in a20 in73n b20 in73p c20 in74p d20 in72p e20 in72n a21 in78p b21 in74n c21 in75p d21 in75n e21 nc a22 in78n b22 in79p c22 in79n d22 tck e22 v ss a23 in76p b23 in76n c23 tdi d23 v ss e23 trst# a24 in77p b24 in77n c24 v ss d24 tdo e24 update# a25 rco4 b25 vss c25 out00p d25 out01p e25 out07n a26 v ss b26 hw_rst# c26 out00n d26 out01n e26 out07p
ocx160 crosspoint switch ? preliminary data sheet 34 [rev. 1.6] 2/20/01 i-cube, inc. f1 out74n g1 out73n h1 out72n j1 out67n k1 out66n f2 out74p g2 out73p h2 out72p j2 out67p k2 out66p f3 out77p g3 out76n h3 out70p j3 out69p k3 out69n f4 out77n g4 out76p h4 out71n j4 out70n k4 out68p f5 rcb6 g5 v dd .pad h5 out71p j5 v dd .core k5 out68n f22 tms g22 out02n h22 v dd .pad j22 v dd .core k22 v dd .core f23 out02p g23 out03p h23 out04p j23 out04n k23 out06p f24 out03n g24 out05p h24 out05n j24 out06n k24 out10p f25 out09n g25 out11n h25 out16n j25 out17n k25 out18p f26 out09p g26 out11p h26 out16p j26 out17p k26 out18n l1 out65n m1 out64p n1 out61p p1 out61n r1 out55p l2 out65p m2 out63n n2 out64n p2 out59p r2 out55n l3 out63p m3 out62n n3 out59n p3 out54n r3 out53p l4 out62p m4 out60n n4 v ss p4 out54p r4 out53n l5 v dd .pad m5 out60p n5 v ss p5 v ss r5 v dd .pad l22 out08n m22 v dd .pad n22 v ss p22 v ss r22 out20p l23 out08p m23 out12p n23 out14p p23 v ss r23 out20n l24 out10n m24 out12n n24 out14n p24 out19n r24 out22n l25 out13p m25 out15p n25 out19p p25 out21n r25 out28p l26 out13n m26 out15n n26 out21p p26 out24n r26 out24p t1 out57p u1 out57n v1 out46n w1 out56n y1 out51n t2 out58n u2 out52p v2 out46p w2 out56p y2 out44p t3 out58p u3 out52n v3 out47n w3 out45n y3 out44n t4 out49p u4 out47p v4 out45p w4 out43p y4 out43n t5 out49n u5 v dd .core v5 v dd .core w5 v dd .pad y5 out41p t22 v dd .pad u22 out23n v22 v dd .core w22 out31p y22 v dd .pad t23 out22p u23 out23p v23 out29n w23 out31n y23 out37n t24 out28n u24 out29p v24 out27n w24 out32n y24 out37p t25 out25p u25 out26p v25 out27p w25 out32p y25 out34n t26 out25n u26 out26n v26 out30p w26 out30n y26 out34p aa1 out51p aa2 out50n aa3 out50p aa4 out41n aa5 rcb3 aa22 out39n aa23 out39p aa24 out36n aa25 out35n aa26 out35p table 22 ocx160 pinout by ball sequence (continued) ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 35 ab1 out48p ac1 out48n ad1 rcb0 ae1 rca6 af1 v ss ab2 out42p ac2 out40p ad2 rcb1 ae2 v ss af2 rca5 ab3 out42n ac3 out40n ad3 v ss ae3 in36n af3 in36p ab4 rcb2 ac4 v ss ad4 rca4 ae4 in34n af4 in34p ab5 v ss ac5 rca3 ad5 in39p ae5 in39n af5 in38n ab6 rca2 ac6 in35p ad6 in37p ae6 in37n af6 in38p ab7 in35n ac7 in31n ad7 in31p ae7 in33n af7 in33p ab8 v dd .in ac8 in30n ad8 in30p ae8 in32p af8 in32n ab9 v dd .core ac9 in29n ad9 in29p ae9 in27n af9 in27p ab10 v ss ac10 in28n ad10 in28p ae10 in26n af10 in26p ab11 v dd .in ac11 in23p ad11 in23n ae11 in25p af11 in25n ab12 in21n ac12 in21p ad12 in22p ae12 in22n af12 in24p ab13 v ss ac13 v ss ad13 in20p ae13 in20n af13 in24n ab14 v ss ac14 in15n ad14 in15p ae14 in19p af14 in19n ab15 v dd .in ac15 in14p ad15 in14n ae15 in18p af15 in18n ab16 in12p ac16 in12n ad16 in13n ae16 in17p af16 in17n ab17 v dd .core ac17 in08n ad17 in13p ae17 in16n af17 in16p ab18 v dd .core ac18 in08p ad18 in10n ae18 in11p af18 in11n ab19 in05p ac19 in06n ad19 in10p ae19 in09p af19 in09n ab20 v dd .in ac20 in05n ad20 in06p ae20 in07p af20 in07n ab21 rco0 ac21 in03n ad21 in03p ae21 in04p af21 in04n ab22 v ss ac22 oe# ad22 rca0 ae22 in02p af22 in02n ab23 out38n ac23 v ss ad23 rca1 ae23 in01n af23 in01p ab24 out38p ac24 v ss ad24 v ss ae24 in00p af24 in00n ab25 out36p ac25 rco1 ad25 rco3 ae25 v ss af25 clkn ab26 out33n ac26 out33p ad26 rco2 ae26 clkp af26 v ss table 22 ocx160 pinout by ball sequence (continued) ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name
ocx160 crosspoint switch ? preliminary data sheet 36 [rev. 1.6] 2/20/01 i-cube, inc. 5.3 pinout by ball name table 23 ocx160 pinout by ball name ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # clkn af25 in20n ae13 in42n a5 in64n a14 out05p g24 clkp ae26 in20p ad13 in42p b5 in64p b14 out06n j24 oe# ac22 in21n ab12 in43n d6 in65n a16 out06p k23 hw_rst# b26 in21p ac12 in43p c6 in65p b16 out07n e25 in00n af24 in22n ae12 in44n a6 in66n b17 out07p e26 in00p ae24 in22p ad12 in44p b6 in66p a17 out08n l22 in01n ae23 in23n ad11 in45n c7 in67n a18 out08p l23 in01p af23 in23p ac11 in45p d7 in67p b18 out09n f25 in02n af22 in24n af13 in46n d8 in68n d17 out09p f26 in02p ae22 in24p af12 in46p e8 in68p c17 out10n l24 in03n ac21 in25n af11 in47n c9 in69n d18 out10p k24 in03p ad21 in25p ae11 in47p c8 in69p c18 out11n g25 in04n af21 in26n ae10 in48n a7 in70n b19 out11p g26 in04p ae21 in26p af10 in48p b7 in70p a19 out12n m24 in05n ac20 in27n ae9 in49n a8 in71n d19 out12p m23 in05p ab19 in27p af9 in49p b8 in71p c19 out13n l26 in06n ac19 in28n ac10 in50n c10 in72n e20 out13p l25 in06p ad20 in28p ad10 in50p b10 in72p d20 out14n n24 in07n af20 in29n ac9 in51n a9 in73n a20 out14p n23 in07p ae20 in29p ad9 in51p b9 in73p b20 out15n m26 in08n ac17 in30n ac8 in52n d10 in74n b21 out15p m25 in08p ac18 in30p ad8 in52p d9 in74p c20 out16n h25 in09n af19 in31n ac7 in53n c11 in75n d21 out16p h26 in09p ae19 in31p ad7 in53p b11 in75p c21 out17n j25 in10n ad18 in32n af8 in54n d11 in76n b23 out17p j26 in10p ad19 in32p ae8 in54p e11 in76p a23 out18n k26 in11n af18 in33n ae7 in55n d12 in77n b24 out18p k25 in11p ae18 in33p af7 in55p c12 in77p a24 out19n p24 in12n ac16 in34n ae4 in56n a10 in78n a22 out19p n25 in12p ab16 in34p af4 in56p a11 in78p a21 out20n r23 in13n ad16 in35n ab7 in57n a12 in79n c22 out20p r22 in13p ad17 in35p ac6 in57p b12 in79p b22 out21n p25 in14n ad15 in36n ae3 in58n b13 nc e21 out21p n26 in14p ac15 in36p af3 in58p a13 out00n c26 out22n r24 in15n ac14 in37n ae6 in59n b15 out00p c25 out22p t23 in15p ad14 in37p ad6 in59p a15 out01n d26 out23n u22 in16n ae17 in38n af5 in60n c13 out01p d25 out23p u23 in16p af17 in38p af6 in60p d13 out02n g22 out24n p26 in17n af16 in39n ae5 in61n c15 out02p f23 out24p r26 in17p ae16 in39p ad5 in61p c14 out03n f24 out25n t26 in18n af15 in40n a3 in62n e15 out03p g23 out25p t25 in18p ae15 in40p b3 in62p d15 out04n j23 out26n u26 in19n af14 in41n a4 in63n d16 out04p h23 out26p u25 in19p ae14 in41p b4 in63p c16 out05n h24 out27n v24
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 37 out27p v25 out51n y1 out74p f2 v dd .core k22 v ss ab14 out28n t24 out51p aa1 out75n e2 v dd .core u5 v ss ab22 out28p r25 out52n u3 out75p e1 v dd .core v5 v ss ac4 out29n v23 out52p u2 out76n g3 v dd .core v22 v ss ac13 out29p u24 out53n r4 out76p g4 v dd .core ab9 v ss ac23 out30n w26 out53p r3 out77n f4 v dd .core ab17 v ss ac24 out30p v26 out54n p3 out77p f3 v dd .core ab18 v ss ad3 out31n w23 out54p p4 out78n c2 v dd .in e7 v ss ad24 out31p w22 out55n r2 out78p c1 v dd .in e12 v ss ae2 out32n w24 out55p r1 out79n d2 v dd .in e16 v ss ae25 out32p w25 out56n w1 out79p d1 v dd .in e19 v ss af1 out33n ab26 out56p w2 rci2 c4 v dd .in ab8 v ss af26 out33p ac26 out57n u1 rci3 c5 v dd .in ab11 out34n y25 out57p t1 rca0 ad22 v dd .in ab15 out34p y26 out58n t2 rca1 ad23 v dd .in ab20 out35n aa25 out58p t3 rca2 ab6 v dd .pad g5 out35p aa26 out59n n3 rca3 ac5 v dd .pad h22 out36n aa24 out59p p2 rca4 ad4 v dd .pad l5 out36p ab25 out60n m4 rca5 af2 v dd .pad m22 out37n y23 out60p m5 rca6 ae1 v dd .pad r5 out37p y24 out61n p1 rcb0 ad1 v dd .pad t22 out38n ab23 out61p n1 rcb1 ad2 v dd .pad w5 out38p ab24 out62n m3 rcb2 ab4 v dd .pad y22 out39n aa22 out62p l4 rcb3 aa5 v ss a1 out39p aa23 out63n m2 rcb4 e3 v ss a2 out40n ac3 out63p l3 rcb5 e4 v ss a26 out40p ac2 out64n n2 rcb6 f5 v ss b2 out41n aa4 out64p m1 rc_clk# b1 v ss b25 out41p y5 out65n l1 rc_en# d3 v ss c3 out42n ab3 out65p l2 rci0 e6 v ss c24 out42p ab2 out66n k1 rci1 d5 v ss d4 out43n y4 out66p k2 rco4 a25 v ss d14 out43p w4 out67n j1 rco0 ab21 v ss d23 out44n y3 out67p j2 rco1 ac25 v ss e5 out44p y2 out68n k5 rco2 ad26 v ss e13 out45n w3 out68p k4 rco3 ad25 v ss e14 out45p v4 out69n k3 tck d22 v ss e17 out46n v1 out69p j3 tdi c23 v ss e22 out46p v2 out70n j4 tdo d24 v ss n4 out47n v3 out70p h3 tms f22 v ss n5 out47p u4 out71n h4 trst# e23 v ss n22 out48n ac1 out71p h5 update# e24 v ss p5 out48p ab1 out72n h1 v dd .core e9 v ss p22 out49n t5 out72p h2 v dd .core e10 v ss p23 out49p t4 out73n g1 v dd .core e18 v ss ab5 out50n aa2 out73p g2 v dd .core j5 v ss ab10 out50p aa3 out74n f1 v dd .core j22 v ss ab13 table 23 ocx160 pinout by ball name (continued) ball name ball # ball name ball # ball name ball # ball name ball # ball name ball #
ocx160 crosspoint switch ? preliminary data sheet 38 [rev. 1.6] 2/20/01 i-cube, inc. 5.4 package dimensions figure 21 ocx160 package ? bottom, top and side views (bottom view) (top view) (side view)
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 39 5.5 package thermal characteristics note : 1. thermal performance values are based on simulation data. table 24 package thermal coefficients package pin count jc (c/w) ja ( c/w) still air pbga 420 1.7 c/w 12 c/w
ocx160 crosspoint switch ? preliminary data sheet 40 [rev. 1.6] 2/20/01 i-cube, inc. 6. power consumption there are two main factors to consider when calculating power consumption for the ocx160: power consumed by the chip power dissipated by the terminating resistors at the switch differential outputs the first component, chip power, consists of three integral elements (refer to figure 22): 1. input power ? this element is fixed (always on) due to the dc current for differential outputs. 2. core power ? this element is the same for lvds or lvpecl outputs. core power is a function of data rate (mb/s) and the number of connection paths through the switch matrix. 3. ouput power ? this element is a fixed amount for each differential output. the value is zero if the output enable (oe#) is disabled or set to off. the second component, termination power, is the power dissipated by the terminating resistors at the switch differential outputs. the value is zero if the output enable (oe#) is disabled or set to off. the following diagram shows the chip power elements (as described above), the formulas used for determining chip power, and the total power consumption as determined by the formula [ chip power + termination power ]. 6.1 power for lvds i/o figure 22 power consumption diagram for the ocx160 using lvds clk output buffer switch matrix input power (always on) core power termination power chip power termination power + r s r s r div 4mw/input + 0.015mw/mbs/connection + 4mw/output + 16mw/output (load) example: worst case = (4mw x 80) + (0.015 mw x 667 x 80) + (4mw x 80) + (16mw x 80) chip power termination power 320mw 800mw 320mw 1280mw + + + = 2.72 watts (total power consumption) = 1440mw + 1280mw output power
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 41 6.2 power for lvpecl i/o figure 23 power consumption diagram for the ocx160 using lvpecl clk output buffer switch matrix input power (always on) core power output power termination power chip power termination power + r s r s r div 4mw/input + 0.015mw /mbs/connection + 4mw/output + 28mw/output (load) example: worst case = (4mw x 80) + (0.015 mw x 667 x 80) + (4mw x 80) + (28mw x 80) chip power termination power 320mw 800mw 320mw 2240mw + + + = 3.68 watts (total power consumption) = 1440mw + 2240mw
ocx160 crosspoint switch ? preliminary data sheet 42 [rev. 1.6] 2/20/01 i-cube, inc. 7. component availability and ordering information 8. glossary clock: a single differential input used to gate data into registers in the output buffer. the input serves all outputs of the ocx. the neighbor input can also be used as a register clock. crosspoint: a single cell controlled by two ram bits. the ram bits are connected in a master-slave configuration to provide an update for programming and changing program information all at once. crosspoint array: an array of crosspoint cells used to connect any input port to any output port. input or output path: the signal flow from pin to array and array to pin. each path has a register with selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on either side of the io buffer. next neighbor: a physically adjacent port can be used as a clock source for an output configured in registered mode. these outputs are grouped in pairs such that the signal being switched through output 0 can be used to clock the signal being switched through output 1, or vice-versa. any single clock or data input signal can be used to clock any other input signal provided they are switched to an appropriate output pair. port: a name followed by a number to identify a pin on the device. rapidconfigure: a parallel programming method for the ocx devices. the rc mode uses 25 dedicated pins to program the crosspoint array and the io buffers. the 25 pins consist of an enable, a clock, four instruction bits, two seven-bit address fields, and a five-bit data field. ocxxxx - ppt family # i/o ports package code pb = ball grid array temperature range blank - commercial (0 c to 70 c) i - industrial (-40 c to +85 c)
ocx160 crosspoint switch ? preliminary data sheet i-cube, inc. [rev. 1.6] 2/20/01 43 revision history date/ version no. description 6/16/2000 revision 1.0 initial release of ? advanced ? data sheet 9/25/00 revision 1.1 additions include rco output pin information, pinout drawing, pinout tables, package dimensions and illustration, duty-cycle diagram, thermal characteristics table, device reset options table, a section on configuring multiple devices, bitstream generation and downloading, jtag information, and power consumption information/illustrations. 10/20/00 revision 1.2 corrections to rc programming table. additions/corrections to multiple tables and timing diagrams. 11/16/00 revision 1.3 updated rapidconfigure read cycle timing diagram so that rco is relative to rc_clk#; rco was previously relative to rc_en#. replaced ? + ? on signal names to ? p ? and ? - ? to ? n ? . corrected rco[4:0] pin locations. changed product status definition from advanced to preliminary. 11/21/00 revision 1.4 corrected pinout drawing and pinout tables to reflect that ? p ? and ? n ? are reversed on out40 to out79. 12/14/00 revision 1.5 corrections to table 22 ? pinout by ball sequence ? to match pinout drawing ? changed ball name on t4 and t5 from out49n and out49p to out49p and out49n resepctively; ball # for in07p corrected from ad20 to ae20. corrections to table 23 ? pinout by ball name ? to match pinout drawing ? corrected in07p ball # from ad20 to ae20; corrected out49p (t5) and out49n (t4) to be out49n (t5) and out49p (t4); corrected out50p (aa2) and out50n (aa3) to be out50n (aa2) and out50p (aa3). 1/20/2001 revision 1.6 changed the v ih , v il , v oh , and v ol minimum and maximum values for lvpecl dc specifications in table 20; added a note below table explaining the current values; changed pass transistor to proprietary high-performance buffering circuit.
ocx160 crosspoint switch ? preliminary data sheet 44 [rev. 1.6] 2/20/01 i-cube, inc. 9. product status definition i-cube ? is a registered trademark and rapidconnect, rapidconfigure, activearray, implieddisconnect, iq, iqx, msx, msxpro, ocx, ocxpro, and psx are trademarks of i-cube, inc. all other trademarks or registered trademarks are the property of their respective holders. i-cube, inc., does not assume any liability arising out of the applications or use of the product described herein; nor does it convey any license under its patents, copyright rights or any rights of others. the information contained in this document is believed to be current and accurate as of the publication date. i-cube reserves the right to make changes, at any time, in order to improve reliability, function, performance or design in order to supply the best product possible. i-cube assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. this product is protected under the u.s. patents: 5202593, 5282271, 5426738, 5428750, 5428800, 5465056, 5530814, 5559971, 5625780, 5710550, 5717871, 5734334, 5781717, 5790048. additional patents pending. ocx160 crosspoint switch data sheet ? rev 1.6, february 2001 copyright ? 1992-2001 i-cube, inc. all rights reserved. unpublished ? rights reserved under the copyright laws of the united states. use of copyright notices is precautionary and does not imply publication or disclosure. i-cube ? , inc. 2605 s. winchester blvd. campbell, ca 95008 usa phone: +(408) 341-1888 ocx160 crosspoint switch data sheet fax: +(408) 341-1899 revision 1.6, february 2001 email: marketing@icube.com document#: mkt-ocx-ds_rev+1+dot+6 internet: http://www.icube.com data sheet identification product status definition advanced formative or in design this data sheet contains the design specifications for product development. specification may change in any manner without notice. preliminary preproduction product this data sheet contains the preliminary data, and supplementary data will be published at a later date. i-cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. no identification full production this data sheet contains final specifications. i-cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. obsolete no longer in production this data sheet contains specifications for a product that has been discontinued by i-cube. the data sheet is provided for reference information only.

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